#Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
#install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1
#OS: Windows 7 6.1
#Hostname: W764-TADIGADAPA
#Implementation: synthesis
$ Start of Compile
#Thu May 22 14:27:35 2014
Synopsys VHDL Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
@N: : | Running in 64-bit mode
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
@N:CD720 : std.vhd(146) | Setting time resolution to ns
@N: : TwoMult_8_Tap_FIR.vhd(21) | Top entity is set to TwoMult_8_tap_FIR.
VHDL syntax check successful!
@N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000")
@N:CD630 : TwoMult_8_Tap_FIR.vhd(21) | Synthesizing work.twomult_8_tap_fir.twomult_8_tap_fir_arch
@W:CD279 : TwoMult_8_Tap_FIR.vhd(93) | Port b_blk of component coef_ram not found on corresponding entity
@W:CD730 : TwoMult_8_Tap_FIR.vhd(407) | Component declaration has 10 ports but entity declares 9 ports
@W:CD638 : TwoMult_8_Tap_FIR.vhd(150) | Signal inp_rden0 is undriven
@W:CD638 : TwoMult_8_Tap_FIR.vhd(151) | Signal inp_rden1 is undriven
@W:CD638 : TwoMult_8_Tap_FIR.vhd(153) | Signal coef_rd0 is undriven
@W:CD638 : TwoMult_8_Tap_FIR.vhd(154) | Signal coef_rd1 is undriven
@W:CD638 : TwoMult_8_Tap_FIR.vhd(166) | Signal ina is undriven
@W:CD638 : TwoMult_8_Tap_FIR.vhd(167) | Signal inb is undriven
@W:CD638 : TwoMult_8_Tap_FIR.vhd(170) | Signal c_addr is undriven
@W:CD638 : TwoMult_8_Tap_FIR.vhd(171) | Signal c_din is undriven
@W:CD638 : TwoMult_8_Tap_FIR.vhd(173) | Signal baddr_coef is undriven
@W:CD638 : TwoMult_8_Tap_FIR.vhd(174) | Signal baddr_inp is undriven
@N:CD630 : Inp_RAM.vhd(17) | Synthesizing work.inp_ram.rtl
@N:CD630 : Inp_RAM_Inp_RAM_0_URAM.vhd(8) | Synthesizing work.inp_ram_inp_ram_0_uram.def_arch
@N:CD630 : smartfusion2.vhd(620) | Synthesizing smartfusion2.ram64x18.syn_black_box
Post processing for smartfusion2.ram64x18.syn_black_box
@N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box
Post processing for smartfusion2.vcc.syn_black_box
@N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box
Post processing for smartfusion2.gnd.syn_black_box
Post processing for work.inp_ram_inp_ram_0_uram.def_arch
Post processing for work.inp_ram.rtl
@N:CD630 : Coef_RAM.vhd(17) | Synthesizing work.coef_ram.rtl
@N:CD630 : Coef_RAM_Coef_RAM_0_URAM.vhd(8) | Synthesizing work.coef_ram_coef_ram_0_uram.def_arch
Post processing for work.coef_ram_coef_ram_0_uram.def_arch
Post processing for work.coef_ram.rtl
@N:CD630 : multacc.vhd(17) | Synthesizing work.multacc.rtl
@N:CD630 : multacc_multacc_0_HARD_MULT_ACC.vhd(8) | Synthesizing work.multacc_multacc_0_hard_mult_acc.def_arch
@N:CD630 : smartfusion2.vhd(695) | Synthesizing smartfusion2.macc.syn_black_box
Post processing for smartfusion2.macc.syn_black_box
Post processing for work.multacc_multacc_0_hard_mult_acc.def_arch
Post processing for work.multacc.rtl
@N:CD630 : multadder.vhd(17) | Synthesizing work.multadder.rtl
@N:CD630 : multadder_multadder_0_HARD_MULT_ADDSUB.vhd(8) | Synthesizing work.multadder_multadder_0_hard_mult_addsub.def_arch
@W:CD275 : multadder_multadder_0_HARD_MULT_ADDSUB.vhd(31) | Component declarations with different initial values are not supported. Port cdin of component macc may have been given a different initial value in two different component declarations
Post processing for work.multadder_multadder_0_hard_mult_addsub.def_arch
Post processing for work.multadder.rtl
Post processing for work.twomult_8_tap_fir.twomult_8_tap_fir_arch
@W:CL252 : TwoMult_8_Tap_FIR.vhd(170) | Bit 0 of signal C_ADDR is floating -- simulation mismatch possible.
@W:CL252 : TwoMult_8_Tap_FIR.vhd(170) | Bit 1 of signal C_ADDR is floating -- simulation mismatch possible.
@W:CL252 : TwoMult_8_Tap_FIR.vhd(170) | Bit 2 of signal C_ADDR is floating -- simulation mismatch possible.
@W:CL252 : TwoMult_8_Tap_FIR.vhd(170) | Bit 3 of signal C_ADDR is floating -- simulation mismatch possible.
@W:CL252 : TwoMult_8_Tap_FIR.vhd(170) | Bit 4 of signal C_ADDR is floating -- simulation mismatch possible.
@W:CL252 : TwoMult_8_Tap_FIR.vhd(170) | Bit 5 of signal C_ADDR is floating -- simulation mismatch possible.
@W:CL240 : TwoMult_8_Tap_FIR.vhd(153) | Coef_rd0 is not assigned a value (floating) -- simulation mismatch possible.
@W:CL240 : TwoMult_8_Tap_FIR.vhd(151) | inp_rden1 is not assigned a value (floating) -- simulation mismatch possible.
@W:CL240 : TwoMult_8_Tap_FIR.vhd(150) | inp_rden0 is not assigned a value (floating) -- simulation mismatch possible.
@W:CL167 : TwoMult_8_Tap_FIR.vhd(424) | Input a_blk of instance U4 is floating
@W:CL167 : TwoMult_8_Tap_FIR.vhd(424) | Input b_blk of instance U4 is floating
@W:CL167 : TwoMult_8_Tap_FIR.vhd(407) | Input a_blk of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 0 of input c_addr of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 1 of input c_addr of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 2 of input c_addr of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 3 of input c_addr of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 4 of input c_addr of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 5 of input c_addr of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 0 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 1 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 2 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 3 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 4 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 5 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 6 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 7 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 8 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 9 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 10 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 11 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 12 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 13 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 14 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 15 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 16 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(407) | Bit 17 of input c_din of instance U3 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 0 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 1 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 2 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 3 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 4 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 5 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 6 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 7 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 8 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 9 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 10 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 11 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 12 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 13 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 14 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 15 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 16 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 17 of input a0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 0 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 1 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 2 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 3 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 4 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 5 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 6 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 7 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 8 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 9 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 10 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 11 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 12 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 13 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 14 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 15 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 16 of input b0 of instance U2 is floating
@W:CL245 : TwoMult_8_Tap_FIR.vhd(381) | Bit 17 of input b0 of instance U2 is floating
@W:CL111 : TwoMult_8_Tap_FIR.vhd(284) | All reachable assignments to inp_rdaddr1(5) assign '0'; register removed by optimization
@W:CL111 : TwoMult_8_Tap_FIR.vhd(256) | All reachable assignments to Coef_rdaddr1(5) assign '0'; register removed by optimization
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 76MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu May 22 14:27:35 2014
###########################################################]
Pre-mapping Report
Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
Linked File: DSP
Printing clock summary report in "D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Semi- Parallel FIR filters\Two Multiplier 8-Tap FIR\TwoMult_8Tap_FIR\synthesis\TwoMult_8_tap_FIR_scck.rpt" file
@N:MF248 : | Running in 64-bit mode.
@N:MF667 : | Clock conversion disabled
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
syn_allowed_resources : blockrams=69 set on top level netlist TwoMult_8_tap_FIR
Clock Summary
**************
Start Requested Requested Clock Clock
Clock Frequency Period Type Group
----------------------------------------------------------------------------------------
System 1.0 MHz 1000.000 system system_clkgroup
TwoMult_8_tap_FIR|clk 404.5 MHz 2.472 inferred Autoconstr_clkgroup_0
========================================================================================
@W:MT530 : multadder_multadder_0_hard_mult_addsub.vhd(108) | Found inferred clock TwoMult_8_tap_FIR|clk which controls 124 sequential elements including U0.multadder_0.U0. This clock has no specified timing constraint which may adversely impact design performance.
Finished Pre Mapping Phase.
@N:BN225 : | Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Semi- Parallel FIR filters\Two Multiplier 8-Tap FIR\TwoMult_8Tap_FIR\synthesis\TwoMult_8_tap_FIR.sap.
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 133MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu May 22 14:27:37 2014
###########################################################]
Map & Optimize Report
Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N:MF248 : | Running in 64-bit mode.
@N:MF667 : | Clock conversion disabled
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Available hyper_sources - for debug and ip models
None Found
@N:MT206 : | Auto Constrain mode is enabled
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
@N: : twomult_8_tap_fir.vhd(239) | Found counter in view:work.TwoMult_8_tap_FIR(twomult_8_tap_fir_arch) inst Coef_rdaddr[4:0]
@N: : twomult_8_tap_fir.vhd(270) | Found counter in view:work.TwoMult_8_tap_FIR(twomult_8_tap_fir_arch) inst inp_rdaddr[4:0]
@N: : twomult_8_tap_fir.vhd(182) | Found counter in view:work.TwoMult_8_tap_FIR(twomult_8_tap_fir_arch) inst inp_wraddr[5:0]
@W:BN132 : twomult_8_tap_fir.vhd(256) | Removing instance Coef_rdaddr2[0], because it is equivalent to instance Coef_rdaddr1[0]
@W:BN132 : twomult_8_tap_fir.vhd(256) | Removing instance Coef_rdaddr2[1], because it is equivalent to instance Coef_rdaddr1[1]
@W:BN132 : twomult_8_tap_fir.vhd(256) | Removing instance Coef_rdaddr2[2], because it is equivalent to instance Coef_rdaddr1[2]
@W:BN132 : twomult_8_tap_fir.vhd(256) | Removing instance Coef_rdaddr2[3], because it is equivalent to instance Coef_rdaddr1[3]
@W:BN132 : twomult_8_tap_fir.vhd(256) | Removing instance Coef_rdaddr2[4], because it is equivalent to instance Coef_rdaddr1[4]
@W:BN132 : twomult_8_tap_fir.vhd(284) | Removing instance inp_rdaddr2[0], because it is equivalent to instance inp_rdaddr1[0]
@W:BN132 : twomult_8_tap_fir.vhd(284) | Removing instance inp_rdaddr2[1], because it is equivalent to instance inp_rdaddr1[1]
@W:BN132 : twomult_8_tap_fir.vhd(284) | Removing instance inp_rdaddr2[2], because it is equivalent to instance inp_rdaddr1[2]
@W:BN132 : twomult_8_tap_fir.vhd(284) | Removing instance inp_rdaddr2[3], because it is equivalent to instance inp_rdaddr1[3]
@W:BN132 : twomult_8_tap_fir.vhd(284) | Removing instance inp_rdaddr2[4], because it is equivalent to instance inp_rdaddr1[4]
@W:BN132 : twomult_8_tap_fir.vhd(256) | Removing instance Coef_rdaddr2[5], because it is equivalent to instance inp_rdaddr2[5]
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -2.47ns 22 / 113
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -2.47ns 21 / 113
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -2.47ns 21 / 113
------------------------------------------------------------
@N:FP130 : | Promoting Net reset_n_c on CLKINT I_12
@N:FP130 : | Promoting Net clk_c on CLKINT I_13
Added 0 Buffers
Added 0 Cells via replication
Added 0 Sequential Cells via replication
Added 0 Combinational Cells via replication
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
#### START OF CLOCK OPTIMIZATION REPORT #####[
Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 119 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
ClockId0001 clk port 119 inp_wraddr[0]
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######]
Writing Analyst data base D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Semi- Parallel FIR filters\Two Multiplier 8-Tap FIR\TwoMult_8Tap_FIR\synthesis\TwoMult_8_tap_FIR.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)
Writing EDIF Netlist and constraint files
@N:BW103 : | Synopsys Constraint File time units using default value of 1ns
@N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF
I-2013.09M-SP1
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
@W:MT246 : inp_ram_inp_ram_0_uram.vhd(89) | Blackbox RAM64x18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT420 : | Found inferred clock TwoMult_8_tap_FIR|clk with period 2.53ns. Please declare a user-defined clock on object "p:clk"
##### START OF TIMING REPORT #####[
# Timing Report written on Thu May 22 14:27:39 2014
#
Top view: TwoMult_8_tap_FIR
Requested Frequency: 395.2 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.
Performance Summary
*******************
Worst slack in design: -0.447
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------------------
TwoMult_8_tap_FIR|clk 395.2 MHz 335.9 MHz 2.531 2.977 -0.447 inferred Autoconstr_clkgroup_0
System 1211.1 MHz 1029.4 MHz 0.826 0.971 -0.146 system system_clkgroup
=================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------
System System | 0.826 -0.146 | No paths - | No paths - | No paths -
System TwoMult_8_tap_FIR|clk | 2.531 1.337 | No paths - | No paths - | No paths -
TwoMult_8_tap_FIR|clk System | 2.531 -0.084 | No paths - | No paths - | No paths -
TwoMult_8_tap_FIR|clk TwoMult_8_tap_FIR|clk | 2.531 -0.447 | No paths - | No paths - | No paths -
=====================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: TwoMult_8_tap_FIR|clk
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------
Coef_rdaddr[0] TwoMult_8_tap_FIR|clk SLE Q Coef_rdaddr[0] 0.094 -0.447
Coef_rdaddr[1] TwoMult_8_tap_FIR|clk SLE Q Coef_rdaddr[1] 0.094 -0.231
Coef_rdaddr[2] TwoMult_8_tap_FIR|clk SLE Q Coef_rdaddr[2] 0.094 -0.127
clr TwoMult_8_tap_FIR|clk SLE Q clr 0.094 -0.084
Coef_rdaddr[3] TwoMult_8_tap_FIR|clk SLE Q Coef_rdaddr[3] 0.094 -0.039
inp_wraddr[0] TwoMult_8_tap_FIR|clk SLE Q inp_wraddr[0] 0.094 -0.031
inp_wraddr[1] TwoMult_8_tap_FIR|clk SLE Q inp_wraddr[1] 0.094 -0.014
inp_wraddr[2] TwoMult_8_tap_FIR|clk SLE Q inp_wraddr[2] 0.094 -0.002
inp_wraddr[3] TwoMult_8_tap_FIR|clk SLE Q inp_wraddr[3] 0.094 -0.002
inp_wraddr[4] TwoMult_8_tap_FIR|clk SLE Q inp_wraddr[4] 0.094 -0.002
===================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
Coef_rdaddr[0] TwoMult_8_tap_FIR|clk SLE EN Coef_rdaddre 2.237 -0.447
Coef_rdaddr[1] TwoMult_8_tap_FIR|clk SLE EN Coef_rdaddre 2.237 -0.447
Coef_rdaddr[2] TwoMult_8_tap_FIR|clk SLE EN Coef_rdaddre 2.237 -0.447
Coef_rdaddr[3] TwoMult_8_tap_FIR|clk SLE EN Coef_rdaddre 2.237 -0.447
Coef_rdaddr[4] TwoMult_8_tap_FIR|clk SLE EN Coef_rdaddre 2.237 -0.447
U2.multacc_0.U0 TwoMult_8_tap_FIR|clk MACC P_SRST_N[0] clr_i_0 2.531 -0.084
U2.multacc_0.U0 TwoMult_8_tap_FIR|clk MACC P_SRST_N[0] clr_i_0 2.531 -0.084
U2.multacc_0.U0 TwoMult_8_tap_FIR|clk MACC P_SRST_N[1] clr_i_0 2.531 -0.084
U2.multacc_0.U0 TwoMult_8_tap_FIR|clk MACC P_SRST_N[1] clr_i_0 2.531 -0.084
inp_wraddr[5] TwoMult_8_tap_FIR|clk SLE D inp_wraddr_s[5] 2.309 -0.031
==============================================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 2.531
- Setup time: 0.293
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.237
- Propagation time: 2.684
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.446
Number of logic level(s): 2
Starting point: Coef_rdaddr[0] / Q
Ending point: Coef_rdaddr[0] / EN
The start point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK
The end point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------
Coef_rdaddr[0] SLE Q Out 0.094 0.094 -
Coef_rdaddr[0] Net - - 0.858 - 6
Coef_rdaddr_n3_i_o3 CFG4 D In - 0.952 -
Coef_rdaddr_n3_i_o3 CFG4 Y Out 0.384 1.336 -
N_102 Net - - 0.548 - 2
Coef_rdaddr_n3_i_o3_RNIG78T CFG3 C In - 1.884 -
Coef_rdaddr_n3_i_o3_RNIG78T CFG3 Y Out 0.196 2.080 -
Coef_rdaddre Net - - 0.603 - 5
Coef_rdaddr[0] SLE EN In - 2.684 -
==========================================================================================
Total path delay (propagation time + setup) of 2.977 is 0.968(32.5%) logic and 2.009(67.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
Path information for path number 2:
Requested Period: 2.531
- Setup time: 0.293
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.237
- Propagation time: 2.684
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.446
Number of logic level(s): 2
Starting point: Coef_rdaddr[0] / Q
Ending point: Coef_rdaddr[1] / EN
The start point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK
The end point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------
Coef_rdaddr[0] SLE Q Out 0.094 0.094 -
Coef_rdaddr[0] Net - - 0.858 - 6
Coef_rdaddr_n3_i_o3 CFG4 D In - 0.952 -
Coef_rdaddr_n3_i_o3 CFG4 Y Out 0.384 1.336 -
N_102 Net - - 0.548 - 2
Coef_rdaddr_n3_i_o3_RNIG78T CFG3 C In - 1.884 -
Coef_rdaddr_n3_i_o3_RNIG78T CFG3 Y Out 0.196 2.080 -
Coef_rdaddre Net - - 0.603 - 5
Coef_rdaddr[1] SLE EN In - 2.684 -
==========================================================================================
Total path delay (propagation time + setup) of 2.977 is 0.968(32.5%) logic and 2.009(67.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
Path information for path number 3:
Requested Period: 2.531
- Setup time: 0.293
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.237
- Propagation time: 2.684
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.446
Number of logic level(s): 2
Starting point: Coef_rdaddr[0] / Q
Ending point: Coef_rdaddr[4] / EN
The start point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK
The end point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------
Coef_rdaddr[0] SLE Q Out 0.094 0.094 -
Coef_rdaddr[0] Net - - 0.858 - 6
Coef_rdaddr_n3_i_o3 CFG4 D In - 0.952 -
Coef_rdaddr_n3_i_o3 CFG4 Y Out 0.384 1.336 -
N_102 Net - - 0.548 - 2
Coef_rdaddr_n3_i_o3_RNIG78T CFG3 C In - 1.884 -
Coef_rdaddr_n3_i_o3_RNIG78T CFG3 Y Out 0.196 2.080 -
Coef_rdaddre Net - - 0.603 - 5
Coef_rdaddr[4] SLE EN In - 2.684 -
==========================================================================================
Total path delay (propagation time + setup) of 2.977 is 0.968(32.5%) logic and 2.009(67.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
Path information for path number 4:
Requested Period: 2.531
- Setup time: 0.293
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.237
- Propagation time: 2.684
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.446
Number of logic level(s): 2
Starting point: Coef_rdaddr[0] / Q
Ending point: Coef_rdaddr[3] / EN
The start point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK
The end point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------
Coef_rdaddr[0] SLE Q Out 0.094 0.094 -
Coef_rdaddr[0] Net - - 0.858 - 6
Coef_rdaddr_n3_i_o3 CFG4 D In - 0.952 -
Coef_rdaddr_n3_i_o3 CFG4 Y Out 0.384 1.336 -
N_102 Net - - 0.548 - 2
Coef_rdaddr_n3_i_o3_RNIG78T CFG3 C In - 1.884 -
Coef_rdaddr_n3_i_o3_RNIG78T CFG3 Y Out 0.196 2.080 -
Coef_rdaddre Net - - 0.603 - 5
Coef_rdaddr[3] SLE EN In - 2.684 -
==========================================================================================
Total path delay (propagation time + setup) of 2.977 is 0.968(32.5%) logic and 2.009(67.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
Path information for path number 5:
Requested Period: 2.531
- Setup time: 0.293
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.237
- Propagation time: 2.684
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.446
Number of logic level(s): 2
Starting point: Coef_rdaddr[0] / Q
Ending point: Coef_rdaddr[2] / EN
The start point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK
The end point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------
Coef_rdaddr[0] SLE Q Out 0.094 0.094 -
Coef_rdaddr[0] Net - - 0.858 - 6
Coef_rdaddr_n3_i_o3 CFG4 D In - 0.952 -
Coef_rdaddr_n3_i_o3 CFG4 Y Out 0.384 1.336 -
N_102 Net - - 0.548 - 2
Coef_rdaddr_n3_i_o3_RNIG78T CFG3 C In - 1.884 -
Coef_rdaddr_n3_i_o3_RNIG78T CFG3 Y Out 0.196 2.080 -
Coef_rdaddre Net - - 0.603 - 5
Coef_rdaddr[2] SLE EN In - 2.684 -
==========================================================================================
Total path delay (propagation time + setup) of 2.977 is 0.968(32.5%) logic and 2.009(67.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------------
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[0] Coef_rddata1[0] 0.000 -0.146
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[1] Coef_rddata1[1] 0.000 -0.146
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[2] Coef_rddata1[2] 0.000 -0.146
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[3] Coef_rddata1[3] 0.000 -0.146
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[4] Coef_rddata1[4] 0.000 -0.146
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[5] Coef_rddata1[5] 0.000 -0.146
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[6] Coef_rddata1[6] 0.000 -0.146
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[7] Coef_rddata1[7] 0.000 -0.146
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[8] Coef_rddata1[8] 0.000 -0.146
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[9] Coef_rddata1[9] 0.000 -0.146
===============================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------
U0.multadder_0.U0 System MACC A[0] inp_rddata1[0] 0.826 -0.146
U0.multadder_0.U0 System MACC A[0] inp_rddata1[0] 0.826 -0.146
U1.multadder_0.U0 System MACC A[0] inp_rddata2[0] 0.826 -0.146
U1.multadder_0.U0 System MACC A[0] inp_rddata2[0] 0.826 -0.146
U0.multadder_0.U0 System MACC A[1] inp_rddata1[1] 0.826 -0.146
U0.multadder_0.U0 System MACC A[1] inp_rddata1[1] 0.826 -0.146
U1.multadder_0.U0 System MACC A[1] inp_rddata2[1] 0.826 -0.146
U1.multadder_0.U0 System MACC A[1] inp_rddata2[1] 0.826 -0.146
U0.multadder_0.U0 System MACC A[2] inp_rddata1[2] 0.826 -0.146
U1.multadder_0.U0 System MACC A[2] inp_rddata2[2] 0.826 -0.146
============================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 0.826
- Setup time: 0.000
+ Clock delay at ending point: 0.000 (ideal)
+ Estimated clock delay at ending point: 0.000
= Required time: 0.826
- Propagation time: 0.971
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : -0.146
Number of logic level(s): 0
Starting point: U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 / A_DOUT[0]
Ending point: U0.multadder_0.U0 / B[0]
The start point is clocked by System [rising]
The end point is clocked by System [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 RAM64x18 A_DOUT[0] Out 0.000 0.000 -
Coef_rddata1[0] Net - - 0.971 - 1
U0.multadder_0.U0 MACC B[0] In - 0.971 -
===================================================================================================================
Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
Path information for path number 2:
Requested Period: 0.826
- Setup time: 0.000
+ Clock delay at ending point: 0.000 (ideal)
+ Estimated clock delay at ending point: 0.000
= Required time: 0.826
- Propagation time: 0.971
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : -0.146
Number of logic level(s): 0
Starting point: U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 / A_DOUT[1]
Ending point: U0.multadder_0.U0 / B[1]
The start point is clocked by System [rising]
The end point is clocked by System [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 RAM64x18 A_DOUT[1] Out 0.000 0.000 -
Coef_rddata1[1] Net - - 0.971 - 1
U0.multadder_0.U0 MACC B[1] In - 0.971 -
===================================================================================================================
Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
Path information for path number 3:
Requested Period: 0.826
- Setup time: 0.000
+ Clock delay at ending point: 0.000 (ideal)
+ Estimated clock delay at ending point: 0.000
= Required time: 0.826
- Propagation time: 0.971
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : -0.146
Number of logic level(s): 0
Starting point: U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 / A_DOUT[2]
Ending point: U0.multadder_0.U0 / B[2]
The start point is clocked by System [rising]
The end point is clocked by System [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 RAM64x18 A_DOUT[2] Out 0.000 0.000 -
Coef_rddata1[2] Net - - 0.971 - 1
U0.multadder_0.U0 MACC B[2] In - 0.971 -
===================================================================================================================
Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
Path information for path number 4:
Requested Period: 0.826
- Setup time: 0.000
+ Clock delay at ending point: 0.000 (ideal)
+ Estimated clock delay at ending point: 0.000
= Required time: 0.826
- Propagation time: 0.971
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : -0.146
Number of logic level(s): 0
Starting point: U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 / A_DOUT[3]
Ending point: U0.multadder_0.U0 / B[3]
The start point is clocked by System [rising]
The end point is clocked by System [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 RAM64x18 A_DOUT[3] Out 0.000 0.000 -
Coef_rddata1[3] Net - - 0.971 - 1
U0.multadder_0.U0 MACC B[3] In - 0.971 -
===================================================================================================================
Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
Path information for path number 5:
Requested Period: 0.826
- Setup time: 0.000
+ Clock delay at ending point: 0.000 (ideal)
+ Estimated clock delay at ending point: 0.000
= Required time: 0.826
- Propagation time: 0.971
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : -0.146
Number of logic level(s): 0
Starting point: U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 / A_DOUT[4]
Ending point: U0.multadder_0.U0 / B[4]
The start point is clocked by System [rising]
The end point is clocked by System [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 RAM64x18 A_DOUT[4] Out 0.000 0.000 -
Coef_rddata1[4] Net - - 0.971 - 1
U0.multadder_0.U0 MACC B[4] In - 0.971 -
===================================================================================================================
Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report for TwoMult_8_tap_FIR
Mapping to part: m2s050fbga896-1
Cell usage:
CLKINT 2 uses
CFG1 4 uses
CFG2 4 uses
CFG3 3 uses
CFG4 4 uses
Carry primitives used for arithmetic functions:
ARI1 6 uses
Sequential Cells:
SLE 113 uses
DSP Blocks: 3
MACC: 3 Mults
I/O ports: 65
I/O primitives: 65
INBUF 21 uses
OUTBUF 44 uses
Global Clock Buffers: 2
RAM/ROM usage summary
Block Rams (RAM64x18) : 2
Total LUTs: 21
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 47MB peak: 133MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu May 22 14:27:39 2014
###########################################################]